Fixed divider for 5.2v
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parent
9712a3f6e7
commit
bded640649
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@ -1,5 +1,6 @@
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{
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{
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"board": {
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"board": {
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"3dviewports": [],
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"design_settings": {
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"design_settings": {
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"defaults": {
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"defaults": {
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"board_outline_line_width": 0.049999999999999996,
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"board_outline_line_width": 0.049999999999999996,
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@ -123,7 +124,8 @@
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"zones_allow_external_fillets": false,
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"zones_allow_external_fillets": false,
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"zones_use_no_outline": true
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"zones_use_no_outline": true
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},
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},
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"layer_presets": []
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"layer_presets": [],
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"viewports": []
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},
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},
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"boards": [],
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"boards": [],
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"cvpcb": {
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"cvpcb": {
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@ -307,18 +309,23 @@
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"rule_severities": {
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"rule_severities": {
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"bus_definition_conflict": "error",
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"bus_definition_conflict": "error",
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"bus_entry_needed": "error",
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"bus_entry_needed": "error",
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"bus_label_syntax": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_bus_conflict": "error",
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"bus_to_net_conflict": "error",
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"bus_to_net_conflict": "error",
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"conflicting_netclasses": "error",
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"different_unit_footprint": "error",
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"different_unit_footprint": "error",
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"different_unit_net": "error",
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"different_unit_net": "error",
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"duplicate_reference": "error",
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"duplicate_reference": "error",
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"duplicate_sheet_names": "error",
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"duplicate_sheet_names": "error",
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"endpoint_off_grid": "warning",
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"extra_units": "error",
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"extra_units": "error",
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"global_label_dangling": "warning",
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"global_label_dangling": "warning",
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"hier_label_mismatch": "error",
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"hier_label_mismatch": "error",
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"label_dangling": "error",
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"label_dangling": "error",
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"lib_symbol_issues": "warning",
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"lib_symbol_issues": "warning",
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"missing_bidi_pin": "warning",
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"missing_input_pin": "warning",
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"missing_power_pin": "error",
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"missing_unit": "warning",
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"multiple_net_names": "warning",
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"multiple_net_names": "warning",
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"net_not_bus_member": "warning",
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"net_not_bus_member": "warning",
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"no_connect_connected": "warning",
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"no_connect_connected": "warning",
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@ -328,6 +335,7 @@
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"pin_to_pin": "warning",
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"pin_to_pin": "warning",
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"power_pin_not_driven": "error",
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"power_pin_not_driven": "error",
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"similar_labels": "warning",
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"similar_labels": "warning",
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"simulation_model_issue": "ignore",
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"unannotated": "error",
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"unannotated": "error",
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"unit_value_mismatch": "error",
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"unit_value_mismatch": "error",
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"unresolved_variable": "error",
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"unresolved_variable": "error",
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@ -345,7 +353,7 @@
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"net_settings": {
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"net_settings": {
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"classes": [
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"classes": [
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{
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{
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"bus_width": 12.0,
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"bus_width": 12,
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"clearance": 0.2,
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"clearance": 0.2,
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"diff_pair_gap": 0.25,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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@ -359,13 +367,15 @@
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"track_width": 0.25,
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"track_width": 0.25,
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"via_diameter": 0.8,
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"via_diameter": 0.8,
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"via_drill": 0.4,
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"via_drill": 0.4,
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"wire_width": 6.0
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"wire_width": 6
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}
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}
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],
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],
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"meta": {
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"meta": {
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"version": 2
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"version": 3
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},
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},
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"net_colors": null
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"net_colors": null,
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"netclass_assignments": null,
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"netclass_patterns": []
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},
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},
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"pcbnew": {
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"pcbnew": {
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"last_paths": {
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"last_paths": {
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@ -381,6 +391,8 @@
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"schematic": {
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"schematic": {
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"annotate_start_num": 0,
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"annotate_start_num": 0,
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"drawing": {
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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"dashed_lines_gap_length_ratio": 3.0,
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"default_line_thickness": 6.0,
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"default_line_thickness": 6.0,
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"default_text_size": 50.0,
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"default_text_size": 50.0,
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"field_names": [],
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"field_names": [],
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@ -412,7 +424,11 @@
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"page_layout_descr_file": "",
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"page_layout_descr_file": "",
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"plot_directory": "",
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"plot_directory": "",
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"spice_adjust_passive_values": false,
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"spice_adjust_passive_values": false,
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"spice_current_sheet_as_root": false,
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"spice_external_command": "spice \"%I\"",
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"spice_external_command": "spice \"%I\"",
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"spice_model_current_sheet_as_root": true,
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"spice_save_all_currents": false,
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"spice_save_all_voltages": false,
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"subpart_first_id": 65,
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"subpart_first_id": 65,
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"subpart_id_separator": 0
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"subpart_id_separator": 0
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},
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},
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